1. Field of the Invention
The present invention relates to an input buffer circuit capable of supplying stable input signals.
2. Description of the Prior Art
Recently, as semiconductor integrated circuit devices are becoming increasingly miniaturized, the input buffer circuit has come to be an important circuit part of such integrated circuit devices. This is because the input buffer circuit determines characteristics, such as the switching level of the input signals supplied from outside sources.
Conventional input buffer circuits are shown in FIGS. 5A, 5B, 6A and 6B. In these figures, symbol A denotes an input signal supplied from an outside source, and B is an output signal obtained from the input buffer circuit. QP1, QP2, QP3, QP4 are P-channel type MOS transistors (hereinafter called PMOSTs), and QN1, QN2, QN3, QN4 are N-channel type MOS transistors (NMOSTs). R11, R12, R13, R14 are parasitic resistances induced by wiring. VCC is the supply voltage, and VSS is the grounding voltage. FIGS. 5A, 5B, 6A and 6B show an input buffer circuit in which four NOT circuits composed of complementary MOS transistors are cascade-connected.
In FIG. 5A, the input buffer circuit is formed on a semiconductor substrate and disposed near the pad to which the supply voltage VCC is applied. Therefore, parasitic resistance barely exists in the wiring connected between the supply voltage VCC and PMOSTs QP1-QP4. On the other hand, in the wiring connected between the grounding voltage VSS and NMOSTs QN1-QN4 there is a parasitic resistance R11.
In FIG. 5B, the input buffer circuit is formed on a semiconductor substrate and disposed near the pad to which the grounding voltage VSS is applied. Since the wiring is short, there is no parasitic resistance between the grounding voltage VSS and NMOSTs QN1-QN4. Between the supply voltage VCC and PMOSTs QP1-QP4, there is a parasitic resistance R12 induced by the wiring.
In FIG. 6A, the input buffer circuit is formed on a semiconductor substrate and disposed near the pad to which the supply voltage VCC is applied. Since the wiring is short, there is no parasitic resistance between the grounding voltage VCC and PMOSTs QP1-QP4. Between the grounding voltage VSS and NMOSTs QN2-QN4, there is a parasitic resistance R13 which is induced by the wiring. Furthermore, the source electrode of NMOST QN1 of the first stage is connected to the grounding voltage VSS through the wiring other than the wiring possessing the parasitic resistance R13. Accordingly, between the NMOST QN1 and grounding voltage VSS, there is parasitic resistance R1.
In FIG. 6B, the input buffer circuit is formed on a semiconductor substrate and disposed near the pad to which the supply voltage VCC is applied. Since the wiring is short, there is no parasitic resistance between the grounding voltage VSS and NMOSTs QN1-QN4. Between the supply voltage VCC and PMOSTs QP2-QP4, there is a parasitic resistance R14 induced by the wiring. The source electrode of PMOST QP1 of the first stage is connected to the supply voltage VCC through the wiring other than the wiring possessing the parasitic resistance R14. Accordingly, there is a parasitic resistance R12 between the PMOST QP1 and the supply voltage VCC.
Meanwhile, in FIG. 6A and FIG. 6B, the complementary MOS transistors of the first stage are connected to the supply voltage VCC and ground voltage VSS through separate wiring respectively in order to decrease the current flowing through the parasitic resistance caused in the circuit after the second stage.
In such prior art, however, the input buffer circuit is constructed by connecting a plurality of NOT circuits composed only of complementary MOS transistors. Accordingly, if the logic voltage of the input signal is an intermediate level between HIGH (or "H") level and LOW (or "L") level, when an input signal A is fed, both the PMOST and NMOST are set in a conductive state at the same time. As a result, a very large current flows from the supply voltage VCC to the grounding voltage VSS. Hence, the power consumption increases. Furthermore, between the grounding voltage VSS and NMOST, there is a parasitic resistance R11 due to the wiring, and the voltage drops due to the current flowing through the parasitic resistance R11. Due to this voltage drop, the switching level of the input signal A deviates from the target value, possibly resulting in malfunction.
This problem is further described below.
The current flowing in the saturated region of an N-channel MOS transistor (IN) is EQU IN=.gamma.N(VG-VSN-VTN).sup.2
where VG is gate voltage, VSN is source voltage, VTN is switching voltage (positive value), and .gamma.N is a constant.
By contrast, the current flowing in the saturated region of P-channel MOS transistor (IP) is EQU IP=.gamma.P(VSP-VG-VTP).sup.2
where VPS is source voltage VTP is switching voltage (negative value), and .gamma.P is a constant.
The switching voltage VTH of the NOT circuit is the gate voltage to achieve the relation of IN=IP, and hence it follows that .gamma.N(VG-VSN-VTN).sup.2 =.gamma.P(VSP-VG-VTP).sup.2. Hence, EQU VTH=(VSP+.alpha.VSN+.alpha.VTN+VTP)/(.alpha.+1) (1)
where constant .alpha. is defined as .alpha.=(.gamma.N/.gamma.P).sup.(1/2).
In circuit design, in the ideal state free from parasitic resistance, the relations EQU VNS=VSS, VSP=VCC
are established, and therefore equation (1) is rewritten as follows at the switching voltage VTH.sub.0 in the ideal state: EQU VTH.sub.0 =(VCC+.alpha.VSS+.alpha.VTN+VTP)/(.alpha.+1) (2)
It is known from equation (2) that the switching voltage VTH.sub.0 in the ideal state is determined by the supply voltage VCC, grounding voltage VSS, switching voltage of NMOST, switching voltage of PMOST, and constant .alpha..
In FIG. 5A, the grounding voltage VSS floats due to voltage drop by the parasitic resistance R11 existing between NMOST and grounding voltage VSS. Therefore VSN, VSP in equation (1) are expressed as follows: EQU VSN=I.sub.0 R11+VSS, VSP=VCC
where I.sub.0 is the current flowing from the supply voltage VCC to the ground voltage VSS, and hence equation (1) may be rewritten as follows: EQU VTH=(.alpha.I.sub.0 R11)/(.alpha.+1)+VTH.sub.0 ( 3)
In FIG. 5B, the supply voltage VCC is lowered due to voltage drop by the parasitic resistance R12 between the PMOST and the supply voltage VCC, and VSN, VSP in equation (1) are expressed as follows: EQU VSN=VSS, VSP=VCC-I.sub.0 R12
and hence equation (1) may be rewritten as follows: EQU VTH=-(.alpha.I.sub.0 R12)/(.alpha.+1)+VTH.sub.0 ( 4)
Equations (3) and (4) indicate the deviation of the input signal A from the switching voltage of the ideal state due to the presence of parasitic resistance.
It is hence a primary object of the invention to suppress the switching level variations or deviations brought about by the parasitic resistance caused by wiring.